In recent years, research and development of nonvolatile storage devices having memory cells formed with variable resistance elements has shown rapid. progress. A variable resistance element is an element with a property that its resistance state reversibly changes between a low resistance state and a high resistance state based on electrical signals, and can store information corresponding to the resistance state in a nonvolatile manner.
Commonly known as a nonvolatile storage device that includes variable resistance elements is a nonvolatile storage device which includes memory cells, referred to as 1T1R (1 Transistor 1 Resistor) memory cells, arranged in a matrix at positions at which bit lines intersect with word lines and source lines that are arranged orthogonally to the bit lines. Here, each of the memory cells includes a MOS transistor and a variable resistance element that are connected in series.
Patent Literature 1 discloses a nonvolatile storage device including 1T1R memory cells in which oxides having a perovskite-type crystalline structure are used as variable resistance elements.
FIG. 18 is a schematic cross-sectional view of a conventional memory cell described in Patent Literature 1. A memory cell 1011 includes: a source region 1002 serving as a first diffusion layer region and a drain region 1003 serving as a second diffusion layer region that are formed on a semiconductor substrate 1001; a selection transistor 1006 including a gate electrode 1005 formed on a gate oxide film 1004; and a variable resistance element 1010 formed by having, between a lower electrode 1007 and an upper electrode 1009, a variable resistance material 1008 whose resistance value changes upon voltage application. Here, the drain region 1003 and the lower electrode 1007 that are electronically connected are connected in series via a conductive via. The upper electrode 1009 is connected via the conductive via to a metal line 1012 serving as a bit line, and the source region 1002 is connected via the conductive via to a metal line 1013 serving as a source line. The gate electrode 1005 is connected to a word line. It is to be noted that Patent Literature 1 discloses Pr1-xCaxMnO3 (PCMO), La1-xSrxMnO3 (LSMO) and so on as the variable resistance material 1008.
In the memory cell 1011 configured as described above, applying a voltage pulse Vpp, a voltage pulse Vss, and a voltage pulse having a predetermined voltage amplitude Vwp to the upper electrode 1009, the source region 1002, and the gate electrode 1005, respectively, changes a resistance state of the variable resistance material 1008 from a low resistance state to a high resistance state, whereas applying the voltage pulse Vss, the voltage pulse Vpp, and a predetermined voltage pulse Vwe to the upper electrode 1009, the source region 1002, and the gate electrode 1005, respectively, changes the resistance state of the variable resistance material 1008 from the high resistance state to the low resistance state.
[Citation List]
[Patent Literature]
[PTL 1] Japanese Unexamined Patent Application Publication No. 2005-25914